VLSI IEEE 2014 - 15
1. Area
delay power efficient carry select adder (CSA)
2. Design
of efficient binary comparators in quantum – Dot Cellular Automata
3. Area
delay power efficient fixed point LMS adaptive filter with low adaptive delay
4. Area
delay efficient Binary adders in QCA.
5. Parallel
AES Encryption Engines for Many-Core Processor Arrays
6. Low-Complexity Multiplier for GF(2m)
Based on All-One Polynomials
7. Split
Radix Algorithm for Length 6mDFT.
8. Area-Efficient
Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast
FIR Algorithm.
9. An
optimized modified booth recorder for efficient design of the Add-multiply
operator .
10. Multifunction
residue architectures for cryptography
11. Fast
sign detection algorithm for the RNS moduli set {2n+1, 2n-1,
2n}
12. Reverse
converter design via parallel – prefix adders : novel components, methodology,
and implementation
13. Low-Power,
High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed
Arithmetic.
14. A
Novel Modulo Adder for 2n-2k- 1Residue Number System
15. Low-Power and Area-Efficient Carry Select Adder
16. Measurement
and Evaluation of Power Analysis Attacks on Asynchronous S-Box.
17. A Low-Power
Single-Phase Clock Multiband Flexible Divider
18. Low
latency successive – cancellation polar decoder architecture using 2-bit
decoding
19. Efficient
integer DCT Architecture for HEVC
20. Critical
path analysis and low complexity implementation of the LMS adaptive algorithm
21. Gate
mapping automation for asynchronous NULL convention Logic circuits.
22.
Design of Digit-Serial FIR Filters: Algorithms,
Architectures, and a CAD Tool
23.
Design of an Error Detection and Data
Recovery Architecture for Motion Estimation Testing Applications
24. Aging
aware reliable multiplier design with adaptive hold logic
25. Analysis
and Design of a Low-voltage Low-power Double-Tail comparator.
26. Universal
set of CMOS gates for the synthesis of multiple valued logic digital circuits.
27. Recursive
approach to the Design of a parallel-self timed adder.
28. Design
of Testable Reversible Sequential Circuits.
29. Gate
Mapping Automation for Asynchronous NULL Convention Logic Circuits.
30. Test
Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes.
31. Period Extension and Randomness Enhancement Using
High-Throughput Reseeding-Mixing PRNG
32. Improved
8-point approximate DCT for image and video compression requiring only 14
additions
33.
High-throughput Multi-standard transform
core supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic.
34. Multicarrier
Systems Based on Multistage Layered IFFT Structure
35. Improvement
of the Security of ZigBee by a New Chaotic Algorithm
36. CORDIC
Based Fast Radix-2 DCT Algorithm
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